1. Field of the Invention
The present invention relates to a laminated structure and a method for its fabrication. The laminated structure is suitable for copper interconnect structure to be formed on a substrate of low dielectric constant material based on a silicon compound. The present invention relates also to a Very-Large-Scale Integrated (ULSI) circuit wiring board and a method for its fabrication. The ULSI circuit wiring board is constructed such that the wiring layer is separated by an interlayer insulator of a low dielectric constant material based on a silicon compound, with a barrier layer interposed between them.
2. Description of the Related Art
The ever-increasing demand for ULSIs with a higher capacity and a lower production cost requires their interconnect structure to have a smaller wiring structure and to be fabricated in a simpler manner. For this reason, the wiring structure in a ULSI is fabricated mainly by the dual-damascene process at the present time. Fabrication of the interconnect structure in a ULSI by the dual-damascene process invariably needs a barrier layer interposed between the wiring layer and the interlayer insulator. This barrier layer prevents copper from diffusing into the interlayer insulator. Without this barrier layer, copper that forms the wiring layer diffuses into the interlayer insulator to bring about insulation failure.
It has been common practice to form the barrier layer from TaN or TiN principally by sputtering. The barrier layer of TaN or TiN needs to be coated with a copper seed layer as a conducting layer because it is poor in conductivity, if the wiring layer is to be formed thereon by electric copper plating.
Fabricating the barrier layer and conducting layer by sputtering, which is a dry process, offsets the advantage of the dual-damascene process, which is a wet process suitable for easy practice and cost reduction.
A possible measure against this situation is to form the barrier layer by electroless plating, which is a wet process. A method for forming the barrier layer by electroless plating is reported in Electrochimica Acta, 44, 1999, pp. 3639-3649. This method involves a step of forming a cobalt layer by sputtering on the surface of the interlayer insulator. The cobalt layer functions as a catalyst layer that helps form the barrier layer of CoWP by electroless plating. The catalyst layer to be formed by sputtering needs a certain thickness to ensure good adhesion between the barrier layer and the interlayer insulator and to ensure uniformity in the barrier layer.
The foregoing method, however, will not reduce the interconnect size of ULSIs beyond the one (equal to or smaller than 100 nm) expected by the industry in near future. Moreover, the foregoing method needs many steps to fabricate the wiring layer and involves processes differing in phase (dry process for sputtering and CVD and wet process for plating). Therefore, it is complex and undesirable costwise. Another disadvantage is that the dry process for sputtering and CVD cannot make a uniform layer as trenches in the wiring layer become narrower than before.
Under the circumstances mentioned above, there has arisen a need for a new method of forming both the barrier layer and the wiring layer only by electroless plating, which is a wet process.